How UCIe Chiplets Enable Optical Interconnects for Next-Generation Data Centers

Chiplets are revolutionizing semiconductor design by allowing heterogeneous integration of diverse process nodes and materials, maximizing performance and efficiency. The emergence of the Universal Chiplet Interconnect Express (UCIe) standard introduces a new era of die-to-die interconnects, offering high bandwidth, low latency, and power-efficient connectivity between chiplets. UCIe also pioneers the inclusion of interfaces compatible with optical links, pushing chiplet technology into the future.

Tackling the Challenges of High-Performance Computing
The demands of high-performance computing (HPC), artificial intelligence (AI), and machine learning (ML) are intensifying the complexity of building large computing systems. Traditional architectures face growing bottlenecks as compute and memory density increases, straining bandwidth and interconnects. Additionally, higher density results in power and cooling constraints that challenge system scalability.

Disaggregation and Optical Solutions
Optical interconnects, known for superior bandwidth compared to copper, present a solution to these challenges. They enable disaggregation of compute and memory resources, allowing flexible and dynamic allocation while enhancing power efficiency and thermal performance.

However, this solution is only temporary. Bandwidth limitations are expected to shift from the data center and rack levels to individual chiplets. Currently, optical interconnects are crucial for chiplet-to-system communication. In the future, copper interconnects within chiplets will need to be replaced by optical alternatives.

Chiplets empower designers to achieve higher performance by enabling heterogeneous integration of cores and 3D-stacked memory. While this improves processing power, it also heightens the need for faster, more efficient, and cost-effective interconnects.

Compute Express Link and UCIe: A Powerful Combination
UCIe complements the compute express link (CXL) protocol, originally developed for PCIe-based rack and data center connections. CXL has now been adapted to function with the UCIe physical layer, extending connectivity beyond chiplets to external systems through optical interconnects. UCIe retimers enable long-distance optical communication, supporting lower latency and power consumption compared to traditional active optical cables and Ethernet solutions.

The UCIe and CXL working groups are collaborating to expand optical I/O specifications. UCIe facilitates resource pooling and aggregation within data centers by linking PCIe/CXL I/O chips to blade servers or even entire racks using integrated optical chips.

Emerging Optical I/O Chiplet Designs
One notable development is the creation of optical I/O (OIO) chiplets that align with the UCIe standard. These chiplets are tailored for next-generation HPC architectures, integrating laser light sources directly into the UCIe-compatible platform. Each OIO chiplet achieves bandwidths of up to 2 Terabits per second (Tbps), equating to 64 lanes of PCIe Gen5.

Another breakthrough involves micro-LED arrays 3D-stacked onto CMOS interface chips, equipped with silicon photodetectors. This architecture facilitates low-power interconnects with power consumption under 1 picojoule per bit (pJ/bit) and transmission distances reaching up to 10 meters. The wide parallel bus structure aligns with the internal architectures of CPUs, GPUs, and large ASICs, eliminating the need for energy-intensive serialization/deserialization (SerDes) interfaces. This innovation supports the separation of GPUs from high-bandwidth memory (HBM), improving thermal management in HPC environments.

Conclusion
UCIe marks a significant step forward in chiplet integration by supporting both copper and optical interconnects. Paired with CXL, UCIe extends optical connectivity to external systems, promoting scalability from chiplets to data center racks. Early implementations of UCIe-based OIO platforms are beginning to materialize, heralding a new phase in advanced HPC and AI-driven architectures.