A schematic can be electrically correct and still become an unreliable PCB. Layout adds physical behavior that the schematic does not show directly: current-return geometry, parasitic resistance and inductance, heat flow, coupling, manufacturability, and mechanical constraints.
These 12 mistakes are common because the board may still “work on the bench.” The real problem appears later as noise, resets, EMI trouble, thermal stress, intermittent communication, difficult assembly, or poor manufacturing yield.
1. Placing decoupling capacitors too far from the IC
A decoupling capacitor is most effective when the high-frequency current loop between the supply pin, capacitor, and return path is compact. A correct capacitor value placed across the board is not equivalent to a correctly placed capacitor.
Better practice: place the local bypass capacitor close to the relevant power/ground pins, keep the connection short, and follow the device datasheet’s layout guidance for sensitive or high-speed devices.
2. Breaking the return path under a fast signal
Signal current travels in a loop. When a trace crosses a split in its reference plane or moves into an area where the return current must take a large detour, the loop area grows. That can increase emissions, susceptibility, and crosstalk.
Better practice: route important fast-edge signals over a continuous reference plane and plan layer transitions so the return path can transition appropriately too.
3. Routing high-current paths like ordinary logic traces
A motor, heater, LED load, relay bank, or switching converter can create voltage drop and heat when its copper path is too narrow or includes unnecessary neck-downs.
Better practice: estimate current, allowable temperature rise and voltage drop; use suitable copper width/area and vias. Check the entire path, including connectors, vias, shunts, ferrite beads, and return copper—not only the longest trace.
4. Ignoring the switching-current loop in power converters
Switch-mode power supplies are especially sensitive to layout. The high di/dt loop around the switching device, diode/synchronous device, and input/output capacitors should be compact according to the regulator manufacturer’s recommended layout.
Better practice: start the PCB from the datasheet/reference layout for the power stage. Do not place the regulator first and then route the critical loop wherever space remains.
5. Using the wrong footprint or orientation
This is one of the most expensive layout errors because DRC may not catch it. Common failures include mirrored connectors, incorrect pin numbering, the wrong package variant, missing exposed pad, incorrect mounting-hole spacing, and unclear polarity.
Better practice: verify critical footprints against the exact manufacturer’s mechanical drawing. For connectors and user-facing parts, review the board from the physical mating direction.
6. Designing to generic DRC defaults instead of the fab process
Clearance, trace width, drill diameter, annular ring, copper-to-edge distance, solder-mask geometry, and slot constraints depend on the manufacturing process you plan to buy.
Altium’s documentation recommends batch DRC before generating final artwork, and PCB manufacturers publish their actual fabrication capabilities. A DRC only proves compliance with the rules you configured.
Better practice: translate your chosen manufacturer’s capabilities into the CAD rules before routing, with margin where practical.
7. Treating ground pour as a magic fix
Filling empty space with copper does not automatically create a good ground system. A ground pour cut by traces, slots, keepouts, or narrow connections can create poor current paths or isolated copper islands.
Better practice: inspect the actual connectivity and return paths after pours are filled. Use stitching vias where they serve a defined purpose, and remove meaningless isolated islands.
8. Mixing noisy and sensitive sections without a placement strategy
Switching nodes, motor drivers, relays, high-current LEDs, DC/DC converters, crystal circuits, RF sections, precision analog inputs, and low-level sensors do not all want the same environment.
Better practice: group the board by function before routing. Keep high-energy switching loops away from sensitive analog nodes. Follow vendor placement/grounding guidance for ADCs, RF devices, clocks and switching regulators rather than applying a simplistic “split every ground” rule.
9. Forgetting test and debug access
A board that is hard to measure is hard to repair. Tiny products still benefit from planned access to power rails, ground, reset, programming pins, and critical buses.
Better practice: provide test pads or accessible vias for key nodes. Make sure a probe can physically reach them without shorting adjacent pins. Keep the programming/debug connector usable after assembly or enclosure installation when service requires it.
10. Putting silkscreen where manufacturing cannot use it
Reference designators printed over pads, polarity marks hidden under components, unreadable text, or labels outside the board outline make assembly and service harder.
Better practice: keep important references readable, mark polarity/orientation clearly, and inspect the final silkscreen with the component bodies and solder mask visible.
11. Ignoring thermal paths
Electrical current and thermal energy share the PCB. Regulators, MOSFETs, LEDs, drivers and processors may need copper area, thermal vias, airflow, heatsinking, or distance from temperature-sensitive components.
Better practice: estimate dissipation before layout. Follow package recommendations for exposed pads and thermal vias, then validate temperature on real hardware under worst credible load and ambient conditions.
12. Exporting fabrication files without inspecting them
The manufacturer builds from the exported manufacturing package, not from the pretty view in your PCB editor. A wrong layer selection, missing board outline, drill-file problem, or stale export can ruin an otherwise correct design.
Better practice: run DRC, generate Gerber/drill files from the final revision, then open the exported files in an independent Gerber viewer. Verify copper, solder mask, silkscreen, outline/cutouts, and plated/non-plated drills.
A pre-route placement checklist
- Connectors are positioned for the real enclosure/cables.
- Critical footprints are checked against datasheets.
- Power converter critical loops are identified.
- Decoupling parts are assigned near the pins they support.
- Noisy and sensitive functional blocks are physically planned.
- Debug/programming access is reserved.
- High-current paths have a copper strategy.
- Mechanical mounting and keepouts are locked.
A post-route review checklist
- Run full DRC with manufacturer-appropriate rules.
- Inspect every un-routed/unconnected item.
- Review reference-plane continuity under critical signals.
- Inspect power and return paths for narrow sections.
- Refill zones and inspect islands/neck-downs.
- Verify polarity and connector orientation manually.
- Inspect solder-mask openings and silkscreen.
- Check copper and components against board edges and mounting hardware.
- Review thermal areas and via patterns.
- Generate manufacturing outputs from the final revision only.
- Inspect exported Gerbers and drill files independently.
Why DRC is necessary but not sufficient
Design-rule checking is excellent at answering questions such as “is this clearance below the configured minimum?” It cannot answer “is this connector facing the correct direction?”, “is this current loop physically sensible?”, or “will this regulator overheat in the enclosure?”
The most reliable review combines automated rules with a deliberate engineering pass through power, signal integrity, mechanics, thermal behavior, assembly, service, and manufacturing outputs.
Continue with the complete schematic-to-Gerbers workflow and the PCB manufacturing review checklist.
Primary references
- Altium Designer — Design Rule Check
- Altium Designer — Verifying Your Board Design
- JLCPCB — Gerber file preparation